Package: covered (0.7.10-5)

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Homepage [covered.sourceforge.net]

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Other Packages Related to covered

depends

recommends

suggests

enhances

dep: libc6 (>= 2.34)

GNU C Library: Shared libraries
also a virtual package provided by libc6-udeb
dep: libtcl8.6 (>= 8.6.0)

Tcl (the Tool Command Language) v8.6 - run-time library files
dep: libtk8.6 (>= 8.6.0)

Tk toolkit for Tcl and X11 v8.6 - run-time files
dep: tklib

standard Tk Library
dep: zlib1g (>= 1:1.1.4)

compression library - runtime

rec: iverilog

Icarus verilog compiler

or verilog

virtual package provided by iverilog

or gplcver (>= 2.12a-1.1)

Verilog simulator

Download covered

Download for all available architectures
Architecture	Package Size	Installed Size	Files
amd64	544.2 kB	2,409.0 kB	[list of files]
arm64	463.7 kB	2,501.0 kB	[list of files]