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[ Source: covered  ]

Paketti: covered (0.7.10-5)

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Muut pakettiin covered liittyvät paketit

  • depends
  • recommends
  • suggests
  • enhances

Imuroi covered

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