Paketti: opensta (0~20191111gitc018cb2+dfsg-1.1)

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Samankaltaisia paketteja:

Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

Muut pakettiin opensta liittyvät paketit

depends

recommends

suggests

enhances

dep: libc6 (>= 2.38)

GNU C Library: Shared libraries
myös näennäispaketti, jonka toteuttaa libc6-udeb
dep: libgcc-s1 (>= 3.0)

GCC support library
dep: libreadline8t64 (>= 6.0)

GNU readline and history libraries, run-time libraries
dep: libstdc++6 (>= 13.1)

GNU Standard C++ Library v3
dep: libtcl8.6 (>= 8.6.0)

Tcl (the Tool Command Language) v8.6 - run-time library files
dep: zlib1g (>= 1:1.1.4)

compression library - runtime

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Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
amd64	882.4 kt	4,104.0 kt	[tiedostoluettelo]
arm64	785.1 kt	4,155.0 kt	[tiedostoluettelo]