Pacote: yosys (0.52-2)

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Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

Outros pacotes relacionados a yosys

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dep: libc6 (>= 2.38)

GNU C Library: Shared libraries
também um pacote virtual fornecido por libc6-udeb
dep: libffi8 (>= 3.4)

Foreign Function Interface library runtime
dep: libgcc-s1 (>= 3.3.1)

GCC support library
dep: libreadline8t64 (>= 6.0)

GNU readline and history libraries, run-time libraries
dep: libstdc++6 (>= 14)

GNU Standard C++ Library v3
dep: libtcl8.6 (>= 8.6.0)

Tcl (the Tool Command Language) v8.6 - run-time library files
dep: python3

interactive high-level object-oriented language (default python3 version)
dep: python3-click

Command-Line Interface Creation Kit - Python 3.x
dep: yosys-abc (>= 0.32-1)

Sequential Logic Synthesis and Verification Algorithms
dep: zlib1g (>= 1:1.2.0)

compression library - runtime

rec: xdot

interactive viewer for Graphviz dot files

Download de yosys

Baixe para todas as arquiteturas disponíveis
Arquitetura	Tamanho do pacote	Tamanho instalado	Arquivos
amd64	6,080.2 kB	25,753.0 kB	[lista de arquivos]
arm64	5,232.7 kB	24,305.0 kB	[lista de arquivos]