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[ 源代码： covered  ]

软件包：covered（0.7.10-5）

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

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下载可用于所有硬件架构的
硬件架构 软件包大小 安装后大小 文件
amd64 544.2 kB2,409.0 kB [文件列表]
arm64 463.7 kB2,501.0 kB [文件列表]