eLxr packages [ bianca ]
[ 源代码： verilator ]
软件包：verilator（5.032-1 以及其他的）
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
其他与 verilator 有关的软件包
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- dep: ccache
- Compiler cache for fast recompilation of C/C++ code
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- dep: g++
- GNU C++ compiler
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- dep: libc6 (>= 2.38)
- GNU C Library: Shared libraries
同时作为一个虚包由这些包填实： libc6-udeb
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- dep: libjs-sphinxdoc (>= 8.1)
- JavaScript support for Sphinx documentation
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- dep: perl
- Larry Wall's Practical Extraction and Report Language
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: sphinx-rtd-theme-common (>= 3.0.2+dfsg)
- sphinx theme from readthedocs.org (common files)
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- rec: libsystemc-dev
- Development files for SystemC library
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer