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[ 源代码： yosys  ]

软件包：yosys（0.52-2）

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Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

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下载可用于所有硬件架构的
硬件架构 软件包大小 安装后大小 文件
amd64 6,080.2 kB25,753.0 kB [文件列表]
arm64 5,232.7 kB24,305.0 kB [文件列表]