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[ 原始碼： covered  ]

套件：covered（0.7.10-5）

covered 的相關連結

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下載原始碼套件 covered：

維護小組：

外部的資源：

相似套件：

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

其他與 covered 有關的套件

  • 依賴
  • 推薦
  • 建議
  • 增強

下載 covered

下載可用於所有硬體架構的
硬體架構 套件大小 安裝後大小 檔案
amd64 544。2 kB2，409。0 kB [檔案列表]
arm64 463。7 kB2，501。0 kB [檔案列表]