eLxr packages [ bianca ]
[ 原始碼： iverilog ]
套件：iverilog（12.0-2 以及其他的）
Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
其他與 iverilog 有關的套件
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- dep: libbz2-1.0
- high-quality block-sorting file compressor library - runtime
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- dep: libc6 (>= 2.35) [amd64]
- GNU C Library: Shared libraries
同時作為一個虛擬套件由這些套件填實： libc6-udeb
- dep: libc6 (>= 2.38) [arm64]
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- dep: libgcc-s1 (>= 3.0)
- GCC support library
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- dep: libreadline8t64 (>= 6.0)
- GNU readline and history libraries, run-time libraries
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- dep: libstdc++6 (>= 13.1)
- GNU Standard C++ Library v3
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- dep: zlib1g (>= 1:1.2.0)
- compression library - runtime
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer