eLxr packages [ bianca ]
[ Источник: yosys ]
Пакет: yosys-abc (0.52-2)
Ссылки для yosys-abc
Исходный код yosys:
- [yosys_0.52-2.debian.tar.xz]
- [yosys_0.52-2.dsc]
- [yosys_0.52.orig-abc.tar.gz]
- [yosys_0.52.orig.tar.gz]
Сопровождающие:
Внешние ресурсы:
- Сайт [github.com]
Подобные пакеты:
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.
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Загрузка yosys-abc
| Архитектура | Размер пакета | В установленном виде | Файлы |
|---|---|---|---|
| amd64 | 4 828,6 Кб | 12 925,0 Кб | [список файлов] |
| arm64 | 4 271,9 Кб | 12 054,0 Кб | [список файлов] |