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软件包：yosys-abc（0.52-2）

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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硬件架构 软件包大小 安装后大小 文件
amd64 4,828.6 kB12,925.0 kB [文件列表]
arm64 4,271.9 kB12,054.0 kB [文件列表]